ꦫꦣꦺꦤ꧀ꦄꦤ꧀ꦠꦱꦺꦤ

PATH: lib / firmware / cirrus

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M_DRC1_OP_LVL��#MBDRC_DRC_1_STRUCT_DRC_OUTPUT_LEVEL���������T��T���M_DRC2_LD_OP_LVL���0MBDRC_DRC_2_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL������������t��@���
M_DRC2_OP_LVL��#MBDRC_DRC_2_STRUCT_DRC_OUTPUT_LEVEL���������y��T���M_DRC3_LD_OP_LVL���0MBDRC_DRC_3_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL���������������@���
M_DRC3_OP_LVL��#MBDRC_DRC_3_STRUCT_DRC_OUTPUT_LEVEL������������D���MBDRC_ENABLE���$MBDRC_MBDRC_CTRL_STRUCT_MBDRC_ENABLE��������������������INPUT_CONDITIONER�����������T���IC_EN��?INPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_ENABLE�����������\���	IC_CH_BAL��AINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_CHAN_BAL�������������d���IC_CH_BALSMHINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_CHAN_BAL_SMOOTH��������������h���IC_MM_XO_ENMINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_MONOMIX_XOVER_ENABLE�������������d���
IC_H_XO_EN�JINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_HALF_XOVER_ENABLE����������/��h���IC_PPU_H_XO_BALKINPUT_CONDITIONER_INPUT_CONDITIONER_PPU_CTRL_STRUCT_INP_COND_HALF_XOVER_BAL�������������\�����	ACTISONIC������������<���ACTISONIC_ENABLE���ACTISONIC_ACTISONIC_ENABLE������������������LIMITER���������T���LI_DRC_LD_OP_LVL���2LIMITER_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL����������!��D���
LI_DRC_OP_LVL��%LIMITER_DRC_1_STRUCT_DRC_OUTPUT_LEVEL�����������&��D���	LI_ENABLE��*LIMITER_LIMITER_CTRL_STRUCT_LIMITER_ENABLE��������������0����
INPUT_ENHANCE�����������\���IE_DRC_LD_OP_LVL���8INPUT_ENHANCE_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL������������&��H���
IE_DRC_OP_LVL��+INPUT_ENHANCE_DRC_1_STRUCT_DRC_OUTPUT_LEVEL���������+��X���	IE_ENABLE��<INPUT_ENHANCE_INPUT_ENHANCE_CTRL_STRUCT_INPUT_ENHANCE_ENABLE��������������������	NOISEGATE�����������X���NG_DRC_LD_OP_LVL���4NOISEGATE_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL������������!��D���
NG_DRC_OP_LVL��'NOISEGATE_DRC_1_STRUCT_DRC_OUTPUT_LEVEL���������&��L���	NG_ENABLE��2NOISEGATE_NOISE_GATE_CTRL_STRUCT_NOISE_GATE_ENABLE��������������T�����VIRTUAL_SUB�������J��4���VS_ENBLVIRTUAL_SUB_VIRTUAL_SUB_ENABLE������������������PDL����
������0���PDL_0_ENABLE���PDL_PDL_0_ENABLE�������������0���PDL_1_ENABLE���PDL_PDL_1_ENABLE���������������8���PDL_0_HI_FRPDL_PDL_0_VARS_HI_FULL_RATIO��������������<���
PDL_0_PTHRESH��PDL_PDL_0_VARS_PIANO_THRESHOLD������������@���
PDL_0_PATTNTN�� PDL_PDL_0_VARS_PIANO_ATTENUATION��������������@���
PDL_0_PBNDSIG�� PDL_PDL_0_VARS_PIANO_BAND_SIGNAL��������������8���PDL_1_HI_FRPDL_PDL_1_VARS_HI_FULL_RATIO��������������<���
PDL_1_PTHRESH��PDL_PDL_1_VARS_PIANO_THRESHOLD������������@���
PDL_1_PATTNTN�� PDL_PDL_1_VARS_PIANO_ATTENUATION��������������@���
PDL_1_PBNDSIG�� PDL_PDL_1_VARS_PIANO_BAND_SIGNAL������������������� �PICL��������������������LOGGER�����������$���ENABLE�
LOGGER_ENABLE�������������$���STATE��LOGGER_STATE��������������$���COUNT��LOGGER_COUNT��������������8���FRMPRWIN���LOGGER_FRAMESPERCAPTUREWINDOW�������������4���
LOGGER_VAR�LOGGER_VARIABLE_VARIABLE���������<�����@���LOGGER_VAR_TYPES���LOGGER_VARIABLE_VARIABLE_TYPES������������ ���DATA���LOGGER_DATA������x������������CLIP_DETECT����������������THRESHOLD_LOGGER�������������,���ENABLE�THRESHOLD_LOGGER_ENABLE�����������4���MAX_TEMP���THRESHOLD_LOGGER_MAX_TEMP�������������<���THRE_LOG_MAX_EXC���THRESHOLD_LOGGER_MAX_EXC��������������@���OVER_TEMP_COUNT THRESHOLD_LOGGER_OVER_TEMP_COUNT��������������<���OVER_EXC_COUNT�THRESHOLD_LOGGER_OVER_EXC_COUNT�����������<���
ABNORMAL_MUTE��THRESHOLD_LOGGER_ABNORMAL_MUTE��������������@���!��PPU���������(���
PPU_ENABLE�PPU_PPU_ENABLE����������������� ��BASS_EXTENSION����������,���ENABLE�BASS_EXTENSION_ENABLE�������������L���B_EXT_MXSHLFGAIN���*BASS_EXTENSION_BASS_EXTENSION_MAXSHELFGAIN����������
��P���
BASS_EXT_GAIN��0BASS_EXTENSION_BASS_EXT_VARS_BASS_EXTENSION_GAIN����������������8���$��SDL��������� ���ENABLE�
SDL_ENABLE�����������������&��
SECURE_ACCESS��������������P���(��TONE_ATTENUATOR����������,���ENABLE�TONE_ATTENUATOR_ENABLE��������������0��"��SDCA������������H���FU21_MR_US_MU_CU���'SDCA_FU21_MAIN_RENDER_USER_MUTE_CURRENT���������	��H���FU21_MR_US_MU_NE���$SDCA_FU21_MAIN_RENDER_USER_MUTE_NEXT������������
��L���FU21_MR_US_VO_CU���)SDCA_FU21_MAIN_RENDER_USER_VOLUME_CURRENT�������������H���FU21_MR_US_VO_NE���&SDCA_FU21_MAIN_RENDER_USER_VOLUME_NEXT������������H���PPU21_MA_PO_NU_C���&SDCA_PPU21_MAIN_POSTURE_NUMBER_CURRENT������������D���PPU21_MA_PO_NU_N���#SDCA_PPU21_MAIN_POSTURE_NUMBER_NEXT���������&��<���SAPU29_PROT_MODE���SDCA_SAPU29_PROTECTION_MODE���������'��@���SAPU29_PROTEC_ST���SDCA_SAPU29_PROTECTION_STATUS�����������-��<���XU22_MR_BYPASS�SDCA_XU22_MAIN_RENDER_BYPASS������������0��4���XU22_FDL_STATUSSDCA_XU22_FDL_STATUS������������1��8���XU22_FDL_SET_IND���SDCA_XU22_FDL_SET_INDEX���������2��<���XU22_FDL_HOS_REQ���SDCA_XU22_FDL_HOST_REQUEST����������3��@���XU24_SPK_SNS_BYP���SDCA_XU24_SPEAKER_SENSE_BYPASS����������<��D���PDE23_TRD_REQ_PS���"SDCA_PDE23_TRANSDUCER_REQUESTED_PS����������=��@���PDE23_TRD_ACT_PS���SDCA_PDE23_TRANSDUCER_ACTUAL_PS���������>��8���TG23_TONE_DIVIDE���SDCA_TG23_TONE_DIVIDER����������^��@���XU22_FDL_MES_OFF���SDCA_XU22_FDL_MESSAGE_OFFSET������������`��@���XU22_FDL_MES_LEN���SDCA_XU22_FDL_MESSAGE_LENGTH�������������������)��WRITE_DETECT�����������������#��EVENT_LOGGER�������������<���EVLOG_HEADER���EVENT_LOGGER_EVENT_LOG_HEADER������������0���EVLOG_EN���EVENT_LOGGER_ENABLED��������������8���
BUFFER_STATUS��EVENT_LOGGER_BUFFER_STATUS������������@���EVLOG_ST_OFF��� EVENT_LOGGER_START_STREAM_OFFSET������������	��8���WAS_DISABLED���EVENT_LOGGER_WAS_DISABLED�����������
��<���EVLOG_TS_SHIFT�EVENT_LOGGER_TIMESTAMP_SHIFT����������������X���*��	ASP_MIXER������������8���ASP_MIX_ENABLE�ASP_MIXER_ASP_MIX_ENABLE�������������������3��VMON_SYNTHESIS�����������,���ENABLE�VMON_SYNTHESIS_ENABLE��������������P���VMS_AC_MOD_IMAX3VMON_SYNTHESIS_ANALOG_CLIPPING_MODULATION_INDEX_MAX������������P���VMS_AC_INT_R���0VMON_SYNTHESIS_ANALOG_CLIPPING_INTERNAL_RESISTOR���������������P���VMS_AC_EXT_R���0VMON_SYNTHESIS_ANALOG_CLIPPING_EXTERNAL_RESISTOR���������������L���
VMS_AC_LOAD_R��,VMON_SYNTHESIS_ANALOG_CLIPPING_LOAD_RESISTOR���������������L���VMS_IMC_CAL_ST�.VMON_SYNTHESIS_IMON_CALIBRATION_IMON_CAL_STATE�������������P���VMS_IMC_CAL_LN�2VMON_SYNTHESIS_IMON_CALIBRATION_CALIBRATION_LENGTH�������������P���VMS_IMC_COR_MAX3VMON_SYNTHESIS_IMON_CALIBRATION_IMON_CORRECTION_MAX������������L���VMS_IMC_APT_RATE���*VMON_SYNTHESIS_IMON_CALIBRATION_ADAPT_RATE�������������`���VMS_IMC_SINE_THR���>VMON_SYNTHESIS_IMON_CALIBRATION_SINEGENERATORSENSE_0_THRESHOLD�������������P���VMS_IMC_IMON_COR���/VMON_SYNTHESIS_IMON_CALIBRATION_IMON_CORRECTION������������8���VMON_SCALING���VMON_SYNTHESIS_VMON_SCALING������������8���IMON_SCALING���VMON_SYNTHESIS_IMON_SCALING������������@���ERROR_VOL_ATTACK���VMON_SYNTHESIS_ERROR_VOL_ATTACK������������@���VMS_ERR_VOL_RLS VMON_SYNTHESIS_ERROR_VOL_RELEASE�������������������4��	BOOT_BEEP������������<���BOOT_BEEP_ENABLE���BOOT_BEEP_BOOT_BEEP_ENABLE������������4���
DSP_BEEP_FREQ��BOOT_BEEP_DSP_BEEP_FREQ�����������8���DSP_BEEP_LEVEL�BOOT_BEEP_DSP_BEEP_LEVEL��������������8���BB_DSP_BEEP_DURBOOT_BEEP_DSP_BEEP_DURATION�����������8���GPIO_BEEP_FREQ�BOOT_BEEP_GPIO_BEEP_FREQ��������������8���GPIO_BEEP_LEVELBOOT_BEEP_GPIO_BEEP_LEVEL�������������4���BEEP_PENDING���BOOT_BEEP_BEEP_PENDING�����������������1��
TWEETER_XOVER��������������8��0��TWEETER_LIMITER���������\���TLI_DRC_LD_OP_LV���:TWEETER_LIMITER_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL����������!��L���TLI_DRC_OP_LVL�-TWEETER_LIMITER_DRC_1_STRUCT_DRC_OUTPUT_LEVEL�����������&��\���
TLI_ENABLE�BTWEETER_LIMITER_TWEETER_LIMITER_CTRL_STRUCT_TWEETER_LIMITER_ENABLE�����������������5��TWEETER_ENHANCE������������<��7��SWDE�������H������(���SWDE_ENSWDE_SWDE_ENABLE��������������,���
SWDE_SW_EN�SWDE_SWDE_SW_ENABLE�����������,���
SWDE_DE_EN�SWDE_SWDE_DE_ENABLE�����������8���SWDE_SW_M_F1_B0SWDE_ST_WIDE_MID_FILT_1_B0������������8���SWDE_SW_M_F1_B1SWDE_ST_WIDE_MID_FILT_1_B1������������8���SWDE_SW_M_F1_B2SWDE_ST_WIDE_MID_FILT_1_B2������������<���SWDE_SW_M_F1_MA1���SWDE_ST_WIDE_MID_FILT_1_MA1�����������<���SWDE_SW_M_F1_MA2���SWDE_ST_WIDE_MID_FILT_1_MA2�����������8���SWDE_SW_M_F2_B0SWDE_ST_WIDE_MID_FILT_2_B0����������	��8���SWDE_SW_M_F2_B1SWDE_ST_WIDE_MID_FILT_2_B1����������
��8���SWDE_SW_M_F2_B2SWDE_ST_WIDE_MID_FILT_2_B2������������<���SWDE_SW_M_F2_MA1���SWDE_ST_WIDE_MID_FILT_2_MA1�����������<���SWDE_SW_M_F2_MA2���SWDE_ST_WIDE_MID_FILT_2_MA2���������
��8���SWDE_SW_M_F3_B0SWDE_ST_WIDE_MID_FILT_3_B0������������8���SWDE_SW_M_F3_B1SWDE_ST_WIDE_MID_FILT_3_B1������������8���SWDE_SW_M_F3_B2SWDE_ST_WIDE_MID_FILT_3_B2������������<���SWDE_SW_M_F3_MA1���SWDE_ST_WIDE_MID_FILT_3_MA1�����������<���SWDE_SW_M_F3_MA2���SWDE_ST_WIDE_MID_FILT_3_MA2�����������8���SWDE_SW_S_F1_B0SWDE_ST_WIDE_SIDE_FILT_1_B0�����������8���SWDE_SW_S_F1_B1SWDE_ST_WIDE_SIDE_FILT_1_B1�����������8���SWDE_SW_S_F1_B2SWDE_ST_WIDE_SIDE_FILT_1_B2�����������@���SWDE_SW_S_F1_MA1���SWDE_ST_WIDE_SIDE_FILT_1_MA1��������������@���SWDE_SW_S_F1_MA2���SWDE_ST_WIDE_SIDE_FILT_1_MA2��������������8���SWDE_SW_S_F2_B0SWDE_ST_WIDE_SIDE_FILT_2_B0�����������8���SWDE_SW_S_F2_B1SWDE_ST_WIDE_SIDE_FILT_2_B1�����������8���SWDE_SW_S_F2_B2SWDE_ST_WIDE_SIDE_FILT_2_B2�����������@���SWDE_SW_S_F2_MA1���SWDE_ST_WIDE_SIDE_FILT_2_MA1��������������@���SWDE_SW_S_F2_MA2���SWDE_ST_WIDE_SIDE_FILT_2_MA2��������������8���SWDE_SW_S_F3_B0SWDE_ST_WIDE_SIDE_FILT_3_B0�����������8���SWDE_SW_S_F3_B1SWDE_ST_WIDE_SIDE_FILT_3_B1�����������8���SWDE_SW_S_F3_B2SWDE_ST_WIDE_SIDE_FILT_3_B2�����������@���SWDE_SW_S_F3_MA1���SWDE_ST_WIDE_SIDE_FILT_3_MA1������������ ��@���SWDE_SW_S_F3_MA2���SWDE_ST_WIDE_SIDE_FILT_3_MA2������������!��4���SWDE_SW_M_SCALESWDE_ST_WIDE_MID_SCALE����������"��4���SWDE_SW_M_SHIFTSWDE_ST_WIDE_MID_SHIFT����������#��4���SWDE_SW_S_SCALESWDE_ST_WIDE_SIDE_SCALE���������$��4���SWDE_SW_S_SHIFTSWDE_ST_WIDE_SIDE_SHIFT���������%��8���SWDE_DE_M_F1_B0SWDE_D_ENH_MID_FILT_1_B0������������&��8���SWDE_DE_M_F1_B1SWDE_D_ENH_MID_FILT_1_B1������������'��8���SWDE_DE_M_F1_B2SWDE_D_ENH_MID_FILT_1_B2������������(��<���SWDE_DE_M_F1_MA1���SWDE_D_ENH_MID_FILT_1_MA1�����������)��<���SWDE_DE_M_F1_MA2���SWDE_D_ENH_MID_FILT_1_MA2�����������*��8���SWDE_DE_M_F2_B0SWDE_D_ENH_MID_FILT_2_B0������������+��8���SWDE_DE_M_F2_B1SWDE_D_ENH_MID_FILT_2_B1������������,��8���SWDE_DE_M_F2_B2SWDE_D_ENH_MID_FILT_2_B2������������-��<���SWDE_DE_M_F2_MA1���SWDE_D_ENH_MID_FILT_2_MA1�����������.��<���SWDE_DE_M_F2_MA2���SWDE_D_ENH_MID_FILT_2_MA2�����������/��8���SWDE_DE_M_F3_B0SWDE_D_ENH_MID_FILT_3_B0������������0��8���SWDE_DE_M_F3_B1SWDE_D_ENH_MID_FILT_3_B1������������1��8���SWDE_DE_M_F3_B2SWDE_D_ENH_MID_FILT_3_B2������������2��<���SWDE_DE_M_F3_MA1���SWDE_D_ENH_MID_FILT_3_MA1�����������3��<���SWDE_DE_M_F3_MA2���SWDE_D_ENH_MID_FILT_3_MA2�����������4��8���SWDE_DE_S_F1_B0SWDE_D_ENH_SIDE_FILT_1_B0�����������5��8���SWDE_DE_S_F1_B1SWDE_D_ENH_SIDE_FILT_1_B1�����������6��8���SWDE_DE_S_F1_B2SWDE_D_ENH_SIDE_FILT_1_B2�����������7��<���SWDE_DE_S_F1_MA1���SWDE_D_ENH_SIDE_FILT_1_MA1����������8��<���SWDE_DE_S_F1_MA2���SWDE_D_ENH_SIDE_FILT_1_MA2����������9��8���SWDE_DE_S_F2_B0SWDE_D_ENH_SIDE_FILT_2_B0�����������:��8���SWDE_DE_S_F2_B1SWDE_D_ENH_SIDE_FILT_2_B1�����������;��8���SWDE_DE_S_F2_B2SWDE_D_ENH_SIDE_FILT_2_B2�����������<��<���SWDE_DE_S_F2_MA1���SWDE_D_ENH_SIDE_FILT_2_MA1����������=��<���SWDE_DE_S_F2_MA2���SWDE_D_ENH_SIDE_FILT_2_MA2����������>��8���SWDE_DE_S_F3_B0SWDE_D_ENH_SIDE_FILT_3_B0�����������?��8���SWDE_DE_S_F3_B1SWDE_D_ENH_SIDE_FILT_3_B1�����������@��8���SWDE_DE_S_F3_B2SWDE_D_ENH_SIDE_FILT_3_B2�����������A��<���SWDE_DE_S_v3_MA1���SWDE_D_ENH_SIDE_FILT_3_MA1����������B��<���SWDE_DE_S_F3_MA2���SWDE_D_ENH_SIDE_FILT_3_MA2����������C��4���SWDE_DE_M_SCALESWDE_D_ENH_MID_SCALE������������D��4���SWDE_DE_M_SHIFTSWDE_D_ENH_MID_SHIFT������������E��4���SWDE_DE_S_SCALESWDE_D_ENH_SIDE_SCALE�����������F��4���SWDE_DE_S_SHIFTSWDE_D_ENH_SIDE_SHIFT�����������I��0���SWDE_XFADE_BAL�SWDE_SWDE_BALANCE������������������/��SHARED_PATCHING_STRUCTURE������������P���SPTCH_MD_SLW_FRM���-SHARED_PATCHING_STRUCTURE_MBDRC_SLEW_N_FRAMES�����������

[+] ..
[-] cs35l63-a1-dsp1-misc-10280e22-spkid3-02-l1u3.bin [edit]
[-] cs35l63-a1-dsp1-misc-10280e84-spkid0-05.wmfw [edit]
[-] cs35l41-dsp1-spk-prot-103c8c4f-spkid0-r0.bin [edit]
[-] cs35l41-dsp1-spk-prot-17aa3855-spkid0-l0.bin [edit]
[-] cs35l63-a1-dsp1-misc-10280e85-spkid3-04-l3u3.bin [edit]
[-] cs35l56-b0-dsp1-misc-10280d33-spkid0-amp1.bin [edit]
[-] cs35l63-a1-dsp1-misc-10280e27-spkid2-06-l1u1.bin [edit]
[-] cs35l41-dsp1-spk-prot-104318d3-spkid0-l0.bin [edit]
[-] cs35l56-b0-dsp1-misc-17aa2349-amp1.bin [edit]
[-] cs35l63-a1-dsp1-misc-10280e1e-spkid3-07-l3u3.bin [edit]
[-] cs35l41-dsp1-spk-prot-103c8ce0.wmfw [edit]
[-] cs35l41-dsp1-spk-prot-10431533-spkid1-r0.bin [edit]
[-] cs35l56-b0-dsp1-misc-10280d33-spkid1-amp4.bin [edit]
[-] cs35l56-b0-dsp1-misc-103c8c53-amp4.bin [edit]
[-] cs35l63-a1-dsp1-misc-10280e27-spkid3-06.wmfw [edit]
[-] cs35l41-dsp1-spk-prot-10431e12-spkid1-r0.bin [edit]
[-] cs35l63-a1-dsp1-misc-10280e3f-spkid1-07-l3u1.bin [edit]
[-] cs35l41-dsp1-spk-prot-103c8a2a-spkid0-l0.bin [edit]
[-] cs35l56-b0-dsp1-misc-103c8c53-amp3.bin [edit]
[-] cs35l54-b0-dsp1-misc-103c8d85.wmfw [edit]
[-] cs35l56-b0-dsp1-misc-17aa392e.wmfw [edit]
[-] cs35l41-dsp1-spk-prot-104317f3-spkid1-l0.bin [edit]
[-] cs35l41-dsp1-spk-prot-10433a60.wmfw [edit]
[-] cs35l41-dsp1-spk-prot-103c8be2.wmfw [edit]
[-] cs35l63-a1-dsp1-misc-10280e20-spkid2-05-l3u1.bin [edit]
[-] cs35l41-dsp1-spk-prot-10431054-spkid1-r0.bin [edit]
[-] cs35l41-dsp1-spk-prot-17aa38b4-spkid1-l0.bin [edit]
[-] cs35l56-b0-dsp1-misc-10280ce3-spkid1-ampl.bin [edit]
[-] cs35l41-dsp1-spk-prot-103c8e3a-spkid0.bin [edit]
[-] cs35l41-dsp1-spk-prot-103c8cde-spkid0.bin [edit]
[-] cs35l41-dsp1-spk-prot-17aa38b6-spkid1-r0.bin [edit]
[-] cs35l41-dsp1-spk-prot-10431454.wmfw [edit]
[-] cs35l41-dsp1-spk-prot-10431c9f-spkid1-r0.bin [edit]
[-] cs35l41-dsp1-spk-prot-103c8a29-spkid1-l0.bin [edit]
[-] cs35l56-b0-dsp1-misc-10280d33-spkid0-amp3.bin [edit]
[-] cs35l41-dsp1-spk-prot-103c8b45.wmfw [edit]
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